Switched capacitor integrators are used in discrete time Sigma Delta analog-to-digital converter (SDADC) circuits, where the number of integrator circuits determines the order of the SDADC. The first integrator in a SDADC determines the overall power, area and performance of the ADC in terms of the effective number of bits (ENOB). The initial integrator circuit uses a sampling capacitor whose size is determined by noise specifications for a given application. The ADC linearity requirements and noise considerations, such as Signal-to-Quantization Noise Ratio (SQNR), determine the bandwidth of the integrator. These considerations often present an undesirable tradeoff between energy efficiency, performance and circuit area, where improved noise and performance specifications often call for larger sampling capacitor sizes, while large sampling capacitors increase the circuit area and power consumption.